Hello, I'm

Valay Saitwadekar

C++ Engineer

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Education

Masters of Science in Computer Science

California State University Fullerton, United States of America

August 2024 - May 2026

CGPA 3.95/4

Bachelors of Engineering in Computer Engineering with Honors in Cyber Security

Shree L. R. Tiwari College of Engineering, University of Mumbai, India

June 2020 - May 2024

CGPA 9.11/10(3.65/4)

Experience

Filtroll International (India) Pvt. Ltd.

Mumbai, India

December 2022 – June 2023

Intern – Software Engineer

  • Implemented inventory management, accounting, and CRM modules using Python and Flask within the ERP system to help the business manage inventory levels and track financial transactions more efficiently, along with custom reports, dashboards, and analytics to provide business insights, reducing manual work by 50% and improving inventory management accuracy by 85%.
  • Formed ERP system requirements and specifications document based on meetings with key business stakeholders to understand their needs and planned development of new capabilities aligned with business growth.
  • Designed a relational database schema in MySQL to organize business data for reports and analysis with stored procedures and database triggers to enforce business logic and data integrity.
  • Created user guides and admin manuals to support onboarding new users and documentation for users covering system navigation and module functions and conducted training to help employees adopt the new ERP tools.

Projects

May 2026 - July 2026
  • Built a market-data engine that ingests the full IEX DEEP feed of 117.8M FIX messages at wire rate, filters to the subscribed instrument, tracks a live L2 order book, generates signals, and broadcasts book updates over SBE-UDP multicast off the hot thread. Sustained 1.21M messages/second with zero NIC-to-engine drops through traffic bursts via non-blocking busy-polled socket reads, and benchmarked a peak of 4.4M messages/second at 226 ns/message with a 6.8 us median order round-trip.
  • Tuned the kernel and CPU to cut worst-case I/O-to-hot tail latency from 630 us to 17 us while holding p50 and p99 flat at 120 ns and 220 ns, targeting the tail rather than the median. Validated the full pipeline through a 3x load burst, sequence-gap injection, and repeated disconnect-reconnect cycles recovering in under 0.30 s, sustaining zero ring drops in every phase while p99 rose only to 250 ns at peak.
  • Cut FIX parse latency to 191 ns/message over 1M+ messages with custom fixed-point numeric parsers, a decimal parser at 4.65 ns running 14x faster than strtod and an integer parser at 7.56 ns running 2x faster than atoi, floating-point-free on the hot path. Layered a complete FIX session engine over it for logon, heartbeat, sequence tracking, and gap recovery, requesting a resend from the server to pull missed messages.
  • Bridged four pinned threads over custom wait-free SPSC ring buffers at a 140 ns round-trip with a zero-copy produce/consume path for 4 KB frames, running an allocation-free, lock-free, cache-aligned, false-sharing-free hot path. Replaced std::map with a cache-conscious flat sorted array to drop order-book update p999 from 50 ns to 20 ns, and discarded an AVX2 SoA book after it measured 64.4 ns against the scalar 41.7 ns.
June 2025 - July 2025
  • Built a C++20 tool for Windows and Linux that performs incremental backups from multiple source directories by detecting file changes using file size and modification time, with a binary metadata cache to prevent redundant copying across runs.
  • Parallelized scanning, hashing, and copying phases using a custom thread pool to efficiently manage concurrent tasks, maximizing resource usage and reducing synchronization time through overlapping operations. Tested with over a million files, maintaining a low memory footprint of just a few megabytes.
  • Designed a disk-aware per-source copy mechanism using thread-safe queues with serialized and parallel modes for peak throughput. Ensured data integrity by updating metadata only after verified copies and enabling automatic retries on failure.
  • Implemented structured logging, UTF-8 support for multilingual file and folder names and configured the system to be fully driven by a user-editable file supporting flexible sync modes, source exclusions, and stale file cleanup.
  • Hands-on work with the 8086 Microprocessor using x86 Assembly. Registers, Memory Addressing, CPU flags, sorting and string operations at the instruction level, BCD to hex conversion, and BIOS Interrupt handling via INT 10h for video services. Builds a direct understanding of how code maps to hardware with no abstractions in between.
  • Turbo Assembler (TASM), 8086 uP Architecture, x86 Assembly
July 2023 - May 2024
  • Launched a website that integrates a CNN model to classify cyclone intensity with 94.5% accuracy using IR(Infrared) images from the MOSDAC website, categorizing cyclones into levels 1 to 5, and providing real-time insights into cyclone severity.
  • Trained a T5 transformer model to generate multilingual safety guidelines and precautionary measures tailored to each cyclone level, enhancing accessibility and improving response strategies for diverse audiences.
  • Integrated OpenWeatherMap API providing additional weather-related information enhancing website’s functionality.
  • Setup Twilio API sending SMS alerts with cyclone intensity and precautionary guidelines, providing timely information to users.
July 2022 - May 2023
  • Developed an Android Application to help people with hearing impairments improve their speaking skills using lip-synced animations and dynamic sound represented in line graphs.
  • Employed GMM – HMM (Hidden Markov Model with Gaussian Mixture Model) to perform Speech Recognition and Waveform Similarity Analysis to identify the accuracy of the words spoken by the user.
December 2022 - December 2022
  • Installed and configured Snort on Kali Linux, modifying its configuration to meet network security needs, and setting up log storage to capture traffic data and monitor real-time network activity.
  • Customized Snort rule configurations to drop malicious ICMP and TCP packets, mitigating unwanted traffic and reinforcing network defenses against reconnaissance and DoS attacks.
  • Executed Nmap scanning from an external machine on the IDS configuration to assess Snort’s performance in identifying and logging irregular traffic, confirming its detection capabilities.

December 2022 - December 2022
  • Simulated UE Nodes equipped with 5G mmWave Antennas and IPv6 interacting with gNB Nodes using MiMo with Beam Forming and TDMA to access internet at 1Gbps Speeds and Low Latency.
  • Operated NS – 3 along with NetAnim and 5G – LENA Modules with NR to visually simulate how the gNB Nodes interact with the UE Nodes to send and receive packets.
  • Visualized and analyzed the antenna design using MATLAB, specifically studying and understanding the modifications made to optimize it for 5G frequency bands and beamforming techniques.
  • Received an Internship Certificate for completing the training and project on 5G.
July 2022 - July 2022
  • Connected a MySQL Database server to an EC2 instance on AWS to run a node.js application.
  • Launched another EC2 instance for NGINX and configured the application to run on this proxy NGINX server.
  • Acquired an Internship Certificate for completing the training and project on AWS.
July 2021 - May 2022
  • Devised an Android Application to provide user-friendly visual password solutions that prioritized optimal security and ease of password entry for individuals with dyslexia, combining visual cues, multi-touch gestures, and customizable features.
  • Built the touch pattern capture and comparison module to record multi-touch gestures accurately on images, enabling intuitive and interactive password creation leveraging gestures such as tapping, swiping, and holding.
  • Innovated a grid overlay on images, serving as a visual guideline for password entry, ensuring accuracy and ease of use.
  • Applied a comparison mechanism to validate entered passwords against stored ones, assuring authentication accuracy.
  • TransactViaMe is a cloud-native, event-driven payment backend platform designed to simulate real-world payment processing workflows, emphasizing scalability, reliability, and observability. The system orchestrates asynchronous payment workflows across authorization, settlement, and ledger services using Java and Python, connected via Kafka with PostgreSQL and Redis to ensure durable and cached state.
  • The platform features high-throughput Kafka pipelines capable of processing 50K+ payment events per minute, with idempotent consumers, retries, and failure recovery, maintaining data integrity during service restarts and load spikes. Automatic horizontal scaling is enabled on AWS EKS using Kubernetes with Horizontal Pod Autoscaler, sustaining API response times under 200 ms under synthetic stress testing with k6 and Locust.
  • Supporting services and tooling are developed in TypeScript, with stress and failure testing conducted across pods and Kafka consumers. Observability is ensured through Prometheus, Grafana, and centralized logging, providing full visibility into system performance, throughput, and resilience.
  • TransactViaMe demonstrates the design and operation of distributed, event-driven backend systems that are scalable, fault-tolerant, and production-ready, which can be easily integrated to any frontend interface.
  • Architected a secure file storage middleware system addressing the absence of unified encryption, access control, and data masking in distributed environments, implementing AES-256-GCM encryption with HKDF-based per-file key derivation so decryption keys never touched the client or persisted unencrypted.
  • Designed a comprehensive role-based access control framework enforcing least privilege across distinct user roles, managing the full identity lifecycle and instantly revoking sessions on any permission change to eliminate outdated access.
  • Developed a tamper-evident audit logging system using an HMAC-SHA256 hash chain to create a single verifiable record of every access event and administrative action, supporting both on-demand and automated background tamper detection.
  • Hardened the system with defense-in-depth controls including TLS 1.2/1.3 with forward-secret cipher suites, CSRF protection, rate limiting, and account lockout policies, mitigating credential stuffing, session hijacking, and man-in-the-middle risks across CLI and browser interfaces.
  • Architected a production-style ETL pipeline using Apache Airflow to automate weather data collection, transformation, and storage, demonstrating real-world data engineering workflow design.
  • Implemented a DAG with independent extraction, transformation, and load tasks, structuring the pipeline so each stage could be scheduled, monitored, and debugged independently.
  • Processed raw JSON API responses into clean, structured weather records covering temperature, humidity, and condition fields, preparing data for reliable long-term storage in PostgreSQL.
  • Orchestrated the full infrastructure with Docker and Docker Compose, containerizing Airflow, PostgreSQL, and pgAdmin to mirror a deployable, scalable data engineering environment.
  • Designed and executed a multi-notebook EDA project integrating customer loyalty history and monthly flight activity records to produce a unified analysis of a fictional airline rewards program.
  • Segmented customer cohorts by loyalty card tier, geography, and tenure to quantify lifetime value distribution, identifying high-ROI retention targets and patterns in card upgrade and cancellation behavior.
  • Produced a comprehensive visual analytics layer covering enrollment trend detection, churn timelines, and points monetization rates, enabling both period-over-period comparison and cross-segment benchmarking.
  • Structured the project with a deliberate separation between analytical output and business interpretation notebooks, demonstrating production-ready organization and the ability to communicate findings to both technical and non-technical audiences.

Coursework

Advanced Algorithm Analysis
Advanced Computer Networking
Application and System Security
Artificial Intelligence
Big Data Analysis
Computer Graphics
Cryptography
Cyber Security and Law
Data Structures
Data Warehouse & Mining
Database Management System
Digital Forensics
Digital Logic & Comp Architecture
Distributed Computing
Ethical Hacking
Internet Programming
Machine Learning
Malware Analysis
Microprocessor
Natural Language Processing
Operating Systems
Operating Systems Design
Security Information Management
Social Media Analytics
Software Design and Architecture
Software Engineering
Software Maintenance
System Programming & Compiler Construction
Theory of Computer Science
Web Security

Skills

Programming Languages
C
C++
Java
Kotlin
Python
R
SQL
HTML/CSS
JavaScript
TypeScript
Shell Scripting
MATLAB
C++ Core
Memory Model
Undefined Behavior
Implementation-Defined Behavior
Move Semantics
Copy Semantics
Rule of 3/5/0
Perfect Forwarding
Value Categories
RAII
Smart Pointers
Allocator Behavior
Custom Allocators
Object Lifetime
Storage Duration
STL Internals
Iterator Invalidation
Virtual Dispatch
VTable Internals
Multiple Inheritance
EBO
CRTP
cv-qualifiers
Casts
Templates & Metaprogramming
SFINAE
Concepts
Constraints
Type Traits
CTAD
Explicit Object Parameters
ADL
Linkage
Name Mangling
ODR
constexpr
consteval
constinit
if constexpr
Structured Bindings
Inline Variables
Lambdas
Ranges
Views
Coroutines
Modules
Exception Handling
noexcept
Concurrency & Synchronization
Lock-free Programming
Wait-free Programming
Atomic Operations
Memory Ordering
Compare and Swap (CAS)
Read-Modify-Write (RMW)
False Sharing
Memory Barriers
SPSC Queue
MPMC Queue
Ring Buffers
Hazard Pointers
Read-Copy-Update (RCU)
Synchronization Primitives
Thread Pools
Task Queues
Concurrent Data Structures
Multithreading
Thread Local Storage
Thread Pinning/Affinity
Double Buffering
Condition Variables
Mutexes
Spinlocks
Futex
Reader-Writer Locks
CPU & System Architecture
Cache Hierarchy
Branch Prediction
Out-of-order Execution
Speculative Execution
x86 Microarchitecture
CPU Pipelining
NUMA Topology
Translation Lookaside Buffer (TLB)
Virtual Memory
SIMD
Prefetching
DRAM Latency
Instruction-Level Parallelism
Superscalar Execution
Hyperthreading
Write Buffers
Store Buffers
OS Scheduling
Kernel & User Space
Memory Management
Microprocessors
Computer Architecture
Power States
Clock Gating
Low Latency & Performance
Hot Path Optimization
Cache-line Alignment
Branchless Coding
Zero-copy Design
Lock-free Data Structures
Cache-conscious Data Structures
Inlining
Vectorization
Loop Unrolling
Aligned Pointers
Return Value Optimization (RVO)
Named-RVO (NRVO)
Memory Footprint Reduction
Stack Allocator
Pool Allocator
Bump Allocator
Fixed-Point Arithmetic
Allocation-Free Hot Path
LTO
GCC/Clang Function Attributes
AVX2/SIMD Intrinsics
Hardware Tuning
CPU/IRQ Affinity
Kernel Bypass
Direct Memory Access (DMA)
Cache Warming
Memory Locking
C/P-State Management
Page Sizing and Huge Pages
Core Isolation
NUMA Tuning
Memory-Mapped I/O
Busy-Polling
Profiling & Debugging
perf
Flamegraphs
KCachegrind
Callgrind
Google Benchmark
Valgrind
gdb
gprof
strace
x64dbg
WinDbg
Locust
k6
Postman
HdrHistogram
ASan/UBSan/TSan
RDTSCP Cycle Timing
Build & Tooling
CMake
Make
Bazel
GTest
Git
GitHub
CI/CD Pipelines
Gradle
Maven
Jenkins
npm
yarn
pip
Test Driven Development
Unit & Integration Testing
Frameworks & Libraries
Spring Boot
FastAPI
Flask
Node.js
NestJS
Django
jQuery
NumPy
pandas
Matplotlib
SciPy
Scikit-Learn
TensorFlow
PyTorch
OpenCV
Databases & Messaging
Kafka
Redis
PostgreSQL
MySQL
Cloud & DevOps
Docker
Kubernetes
AWS
Prometheus
Grafana
Event-driven Architecture
Terraform
Ansible
ELK Stack
Nginx
Reverse Proxy
Security & Forensics
Ghidra
Burp Suite
OWASP ZAP
Wireshark
Tcpdump
IDS/IPS
Snort
Nmap
Security Incident Response
Risk Management
Systems & Low-level Tools
Linux
Filesystems
WSL
Kali Linux
SysInternals
IDEs & Developer Tools
Visual Studio
Android Studio
Eclipse
Figma
Blender
Jira
PowerToys

Extra Curricular

Research Presentation at RESCON 2024

IIT Bombay Research Park

13th January 2024
  • Qualified for Poster Presentation Round among the top 100+ abstracts in Research Presentation.

Entrepreneurship Cell (E–Cell) SLRTCE

2022 – 2023

Vice President

  • Scored the 26th spot in the National Entrepreneurship Challenge (NEC) 2022 conducted by IIT Bombay out of the 300 participating college across India.
  • Organized seminars and worked with the team to grow the reach to all 7 Engineering departments in the college.

Research Presentation at RESCON 2023

IIT Bombay Research Park

4th February 2023
  • Placed 4th in the Podium Presentation Round, out of the top 100+ abstracts in the Research Presentation.

18th Aavishkar Inter-collegiate/Institute/Department Research Convertion(Zonal Round)

University of Mumbai at Vivekanand Education Society's Institute of Technology, Chembur

15th December 2023
  • Presented DISHA Project.
  • Reached 2nd Round amongst 1000+ participating projects.

Computer Society of India (CSI) Committee SLRTCE

2022 – 2023

Active Member and Volunteer

  • Volunteered as an Active Member of the Computer Society of India (CSI) Committee SLRTCE for 2022-23 promoted and coordinated events like the ChatGPT Challenge and Meta Summit.

17th Aavishkar Inter-collegiate/Institute/Department Research Convertion(Zonal Round)

University of Mumbai at Shah and Anchor Kutchhi Engineering College, Chembur

23rd December 2022
  • Presented SIPHI Project.

Computer Engineering Department Newsletter “Velocity”

2021 – 2022

Lead Editor

  • Edited the newsletter showcasing presentation and documentation skills.

Get in Touch

Contact Me

ReachValay@Gmail.com